System and method for clock domain grouping using data path relationships

ABSTRACT

A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

RELATED APPLICATIONS

[0001] [Not Applicable]

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] [Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[0003] [Not Applicable]

BACKGROUND OF THE INVENTION

[0004] Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexors, logic circuits, etc. A given chip design may have thousands of flip-flops scattered throughout the chip.

[0005] In order to effectively and efficiently test a given chip, certain test features are typically incorporated into the chip design for testing purposes. Before a chip is actually taped out and manufactured, the chip design is first simulated in software using various simulation tools such as, for example, an Automatic Test Pattern Generation (ATPG) tool. By simulating the design of the chip, the design features of the chip may be thoroughly tested before the expense and time of actually manufacturing the chip is incurred.

[0006] Pattern verification is a critical phase in testing of chips. A scan pattern is a digital string of binary ones and zeros that may be shifted through a scan chain of flip-flops in the chip design. Every scan pattern cycle is composed of two phases. The first phase is the load-unload phase where new data is shifted into the scan chains of flip-flops. The second phase is the capture phase where the data is captured into the flip-flops by applying a clock pulse.

[0007] Typically, the flip-flops in a digital integrated circuit design are designed such that they have normal data inputs and outputs (D and Q) and test inputs such as TI (test data input) and TE (test enable input). During simulation, the flip-flops may be placed in the scan test mode by enabling the TE input. Data may then be clocked into the flip-flops through the TI input instead of the normal D data input. During scan testing, the flip-flops of the chip are chained together to form multiple scan chains. The output Q of a given flip-flop is connected to the input TI of a next flip-flop. Each scan chain may comprise, typically, 5000 to 10,000 flip-flops.

[0008] The length of the load-unload phase is equal to the length of the longest scan chain of flip-flops. In multimillion gate designs, the longest chain may have thousands of flip-flops. Most of the time simulating the scan patterns through the scan chains is spent shifting the data into and out of the scan chains. To ensure proper behavior of the scan chains, the first test applied to the chip design is Chain Test which consists of shifting in and out a predetermined bit pattern (e.g., 0011).

[0009] Timing analysis may be performed on the simulation of the design of the chip by using external scan test clocks to clock the various clock domains (flip-flops and other digital logic that use a same clock). For every clock domain, an external scan test clock may be input at a port of the chip and used to clock the corresponding clock domain by by-passing the corresponding internal clock for the clock domain. The timing analysis identifies any capture mode violations such that the design may be fixed to eliminate the violations. However, such simulation and testing often require many scan test clocks using many ports of the chip in order to test all of the clock domains, especially for large chips with millions of gates. Even if certain ports of the chip are externally tied together at the chip level to the same scan clock, a single port of the chip is still needed for each clock domain within the chip. In the capture mode during timing analysis, scan patterns are clocked into the D inputs of the flip-flops instead of the TI inputs.

[0010] One of the major issues in generating tests for multi-million gate chip designs is how to reduce ATPG pattern count in order to fit in the tester memory. Designs with multiple clock domains pose a great challenge given that, by default, ATPG tools toggle one clock at a time during a capture mode. The number of scan clocks that may be required to be provided from the chip level may be very large if the chip design has a large number of internal clock domains. Each scan clock operates at the same frequency using the same waveform. Some clock domains may be grouped together soley based on designer input, but this has proven to cause timing problems if the clock domains that are grouped are not truly independent (i.e., share no data paths).

[0011] Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

[0012] A method is provided, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, internal to the chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design, by-passing the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

[0013] A system is provided and used in a simulation of a design of a digital integrated circuit chip to limit a number of scan test clocks and chip ports used for testing the chip. The system comprises an automatic test pattern generation (ATPG) tool to identify clock domains within the design of the chip that are independent of each other, and to group, internally to the chip design, the independent clock domains to form clock domain groups. The clock domain groups are stored as a clock grouping report in the ATPG tool. A timing analysis tool is also provided to perform timing analysis of the design of the chip by clocking the clock domain groups each with an independent scan test clock that originates externally to the chip design. Capture mode violations are generated by the timing analysis and are used to go back and form new clock domain groups, thereby repeating the process until no capture mode violations are generated.

[0014] These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a schematic block diagram of an exemplary simulation and test system in accordance with an embodiment of the present invention.

[0016]FIG. 2 is a flowchart of a method operating on the test system of FIG. 1 to limit a number of scan test clocks and chip ports used for testing a digital integrated circuit chip in accordance with an embodiment of the present invention.

[0017]FIG. 3 is an exemplary schematic block diagram illustrating independent clock domains and dependent clock domains of a chip design in accordance with an embodiment of the present invention.

[0018]FIG. 4 is an exemplary schematic block diagram of a chip design illustrating the internal grouping of independent clock domains and the internal by-passing of internal clocks in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] Aspects of the present invention provide a method and system to limit a number of scan test clocks and chip ports used for testing a digital integrated circuit chip having millions of gates.

[0020]FIG. 1 is a schematic block diagram of an exemplary simulation and test system 5 in accordance with an embodiment of the present invention. The system 5 comprises an Automatic Test Pattern Generating (ATPG) tool 10 and a Timing Analysis (TA) tool 20. In an embodiment of the present invention, at a top level, the ATPG tool 10 inputs a set of initial chip design definition files 15 and capture mode violation information 24, and generates a clock grouping report 14. The clock grouping report 14 is used to generate a modified set of chip design definition files 16. The set of initial chip design definition files 15 completely defines the initial design of a digital integrated circuit chip. The modified set of chip design definition files 16 completely defines a modified version of the digital integrated circuit chip.

[0021] The TA tool 20 inputs the modified set of chip design definition files 16 and outputs the capture mode violation information 24. The capture mode violation information 24 is then fed back and input to the ATPG tool 10 and a new grouping report 14 may be generated.

[0022] In accordance with an embodiment of the present invention, the ATPG tool 10 comprises at least one processor module 11 and at least one memory module 12. The ATPG tool 10 also comprises at least one software simulation module 13 that is stored in the at least one memory module 12 and is executed on the at least one processor module 11. In an embodiment of the present invention, the ATPG tool 10 generates the clock grouping report 14. The clock grouping report 14 is used to generate the modified set of chip design definition files 16. The ATPG tool 10 may be, for example, a commercial Tetramax ATPG tool from Synopsis, or may be some other ATPG tool.

[0023] In accordance with an embodiment of the present invention, the TA tool 20 comprises at least one processor module 21 and at least one memory module 22. The TA tool 20 also comprises at least one software timing analysis module 23 that is stored in the at least one memory module 22 and is executed on the at least one processor module 21. In an embodiment of the present invention, the TA tool 20 generates the capture mode violation information 24. The capture mode violation information 24 is fed back to the ATPG tool 10 and is used to generate a new clock grouping report 14.

[0024] Referring to FIG. 2, method 100 defines a process to limit a number of scan test clocks and chip ports used for testing the design of the chip with the system 5, for example. In step 110, the initial design of the chip internally by-passes, at the core level, all internally generated clocks. In step 120, the ATPG tool 10 inputs the initial design definition files 115 and attempts to identify the clock domains that are independent (i.e., share no data paths between them). In step 130, the ATPG tool 10 forms clock domain groups based on the independence analysis. The clock domain groups are stored in the clock grouping report 14. The design of the chip is again modified internally to tie each clock domain group to a single port of the chip. In an embodiment of the present invention, the modification of the design of the chip may be performed by the ATPG tool 10. As an alternative, the actual modification of the design of the chip may be performed off-line using some other tool such as a computer-based chip design tool.

[0025] In step 150, the TA tool 20 inputs the modified set of design definition files 16 and goes into a capture mode. In step 160, while in the capture mode, the TA tool 20 performs a timing analysis to determine if there are any capture mode violations in the modified design. Capture mode violations are typically caused by timing violations in the design of the chip.

[0026] For example, referring to FIG. 3, in the capture mode, scan pattern data may be clocked into flip-flop register 230 by an external scan clock 270 provided by the ATPG tool 10. Data appears at the input of flip-flop register 240 after passing through and being modified by logic cloud 235. Data may next be clocked into flip flop register 240 by an external scan clock 280 provided by the ATPG tool 10. If the data captured in flip-flop register 240 does not match the expected data based on the original scan pattern data clocked into flip-flop register 230 and the effects of the logic cloud 235, then at least one capture mode violation has occurred. Assuming the flip-flop registers 230 and 240 were previously tested in a scan mode, then the capture mode violation is likely due to a timing problem in the logic cloud 235.

[0027] As a further example, if flip-flop register 230 and flip-flop register 240 were clocked at the same time by the same scan test clock 270, then capture mode violations would almost certainly occur since the two flip-flop registers do not constitute independent clock domains. In other words, since the two flip-flop registers are connected by a data path (i.e., the logic cloud 235), the data captured in flip-flop register 240 will not be the expected data since the scan pattern data being clocked into flip-flop register 230 and going through logic cloud 235 has not had time to properly settle down and become valid before flip-flop register 240 is clocked.

[0028] Therefore, it may be seen that, during timing analysis, clock domains that are not independent should be clocked by different clocks at different times to avoid capture mode violations. FIG. 3 shows that scan test clock 270 is coupled to clock domain 230 and clock domain 250 which are independent of each other (i.e., no data path between them). Also, scan test clock 280 is coupled to clock domain 240 and clock domain 260 which are independent of each other. As a result, it may be seen that independent clock domains may be grouped together and clocked by the same scan test clock during capture mode timing analysis. Any capture mode violations that occur are stored in the at least one memory module 22 in TA tool 20.

[0029] Step 170 checks for capture mode violations. If there are no capture mode violations, then the modified design of the chip is good and the previously determined clock domain groups may be frozen as part of the design. However, if there are any capture mode violations, then the clock domain groups are not truly independent according to the design. As a result, the process is repeated, using the capture mode violation information to try to form clock domain groups that are truly independent.

[0030] In an embodiment of the present invention, before the method 100 is performed, a scan test mode is entered and the scan chain functionality of the chip design is verified. The ATPG tool 10 may be used during the scan test mode to verify the scan chains.

[0031] Once there are no more capture mode violations, the design of the chip may be frozen, having the internal clock domain groupings and by-pass circuitry as part of the design of the chip at the core level.

[0032]FIG. 4 is an exemplary schematic block diagram of a resultant chip design illustrating the internal grouping of independent clock domains and the internal by-passing of internal clocks at the core level, in accordance with an embodiment of the present invention. Various clock groups have been formed (e.g., clock group 370) based on the clock domain independence analysis performed by the system 5 using the method 100. The chip design 200 comprises a clock block 310 with internal clock generating circuitry (e.g., PLLs 320 and clock logic 330). The clock logic may include various divider circuitry, gates, etc. The clock block 310 also comprises one mux 350 for each internally generated clock domain 360. The muxes 350 are used to by-pass the internal clocks of the chip design 200 and pass the scan test clocks 340 (by-pass clocks) during testing in the capture mode.

[0033] The independent clock domains (e.g., 370) are grouped together internally to the chip design (at the core level) and are tied together at ports of the chip (e.g., port 371). Each clock domain group is tied to one chip port. As a result, the number of scan test clocks and chip ports used for testing is greatly reduced. In a typical chip design, there may be approximately 100 clock domains. Embodiments of the present invention may limit the number of scan test clocks and chip ports used for testing to only ten (i.e., as much as a factor of 10 or more).

[0034] After a chip is actually built based on the final chip design, the chip may be tested by going into the capture mode using the same scan patterns used in testing of the simulated chip design. Only the outputs of the chip are tested for the expected results.

[0035] In summary, aspects of the present invention provide simulating a design of a digital integrated circuit chip to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together to form clock domain groups at the core level of the chip design. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design, by-passing the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

[0036] While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims. 

What is claimed is:
 1. A method, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing said chip, said method comprising: identifying clock domains within said design of said chip that are independent of each other; grouping said independent clock domains together, within said design of said chip, to form at least one clock domain group; and performing a timing analysis of said design of said chip by, at least in part, clocking said at least one clock domain group with an independent scan test clock, said scan test clock originating externally to said design of said chip, and testing for any capture mode violations in said design of said chip resulting from said clocking.
 2. The method of claim 1 further comprising repeating said identifying, said grouping, and said performing by using information from said any capture mode violations previously found.
 3. The method of claim 1 further comprising: entering a scan test mode before said identifying; and verifying scan chain functionality of said chip design during said scan test mode.
 4. The method of claim 1 further comprising internally by-passing at least one internal clock of said design of said chip with said independent scan test clock.
 5. The method of claim 1 further comprising changing said design of said chip to tie said at least one clock domain group to a single port of said chip, and to by-pass at least one internal clock of said chip with said independent scan test clock, originating externally to said chip and being input to said chip at said single port.
 6. The method of claim 1 wherein said identifying and said grouping is accomplished using an automatic test pattern generation (ATPG) tool.
 7. The method of claim 3 wherein said entering and said verifying is accomplished using an automatic test pattern generation (ATPG) tool during a scan test mode of said simulation.
 8. The method of claim 1 wherein said performing is accomplished using a timing analysis tool during a capture mode of said simulation.
 9. The method of claim 1 wherein said clock domains comprise at least one of flip-flops and gates.
 10. A system, used in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing said chip, said system comprising: a first tool to identify clock domains within said design of said chip that are independent of each other, and to group said independent clock domains to form at least one clock domain group that is stored in a clock grouping report within said first tool; and a second tool to perform a timing analysis of said design of said chip by, at least in part, clocking said at least one clock domain group with an independent scan test clock, said scan test clock originating externally to said design of said chip, and generating any capture mode violation information of said design of said chip resulting from said clocking.
 11. The system of claim 10 wherein said design of said chip is modified based on, at least in part, said clock grouping report.
 12. The system of claim 10 wherein said design of said chip is modified based on, at least in part, said any capture mode violation information.
 13. The system of claim 10 wherein said first tool comprises an automatic test pattern generation (ATPG) tool, and wherein said ATPG tool comprises: at least one processor module; at least one memory module; and at least one software simulation module residing in said at least one memory module and executed by said at least one processor module.
 14. The system of claim 10 wherein said second tool comprises a timing analysis tool, and wherein said timing analysis tool comprises: at least one processor module; at least one memory module; and at least one software timing analysis module residing in said at least one memory module and executed by said at least one processor module.
 15. The system of claim 10 wherein said first tool inputs at least one chip design file corresponding to an initial design of said chip before performing any grouping of said clock domains.
 16. The system of claim 10 wherein said second tool inputs at least one modified chip design file corresponding to a modified design of said chip after said first tool performs any grouping of said clock domains.
 17. The system of claim 10 wherein at least one modified chip design file is generated within said first tool.
 18. The system of claim 10 wherein at least one modified chip design file is generated offline and outside of said first tool.
 19. The system of claim 10 wherein said first tool inputs said any capture mode violation information.
 20. The system of claim 10 wherein said clock domains comprise at least one of flip-flops and gates.
 21. The system of claim 10 wherein a resultant modified design of said chip comprises: said at least one clock domain group tied to a single port of said chip such that said clock domain group may be clocked by an external scan clock signal input to said single port; and said clock domains of said at least one clock domain group each internally connected to a by-pass multiplexor within said chip design to by-pass at least one internal clock of said design of said chip and to pass said external scan clock signal input to said single port, during simulation and testing of said chip, to said clock domains. 